How to create adaptors between modeling abstraction levels | EDA Edition

In the ESL world, there seems to be many abstraction levels as the standardisation has still not strongly convince the designers working at various levels of design cycles. The SoC architect may have different views about system and would like to have detailed approximation, although a verification person may like to have something highly abstracted so that the simulation performance is high. Similarly, the firmware developer would like to have higher abstraction at many levels but may like to have some approximations in some models.

Hence there is a requirement to have adapters which converts one protocol to another protocol without missing the appropriate information (command, transactions..). I found a good article which talks about this need and possible implementations -

How to create adaptors between modeling abstraction levels EDA Edition

SystemVerilog for verification

Recently, we jumped to Systemverilog methodology for verification and had a training on Systemverilog, as well. An extensive training which covered design aspects in a day and then verification aspects in next 2 days. 

Some of the links on Systemverilog which can be very helpful -

1. Asicguru -> A very nice tutorial on Systemverilog.
2. Testbench.in -> A website which has many pages on Systemverilog and describes concepts pretty well. It also has very good tutorial on UVM methodology for verification.
3. A tutorial on Systemverilog -> A tutorial which can be referenced.
4. A quick go through on Systemverilog -> pretty nice short and sweet tutorial.

Key features of Systemverilog are -

    -> Classes
    -> Interfaces
         -> Clocking blocks
    -> Events - more what is available in Verilog.
    -> SV Assertions
    -> Coverage
    -> SV Randomization

SPEAr on youtube.....

Our contributions and result is as follows in a bigger, global environment -

Wish to see a lot more customers :-)