SystemVerilog for verification

Recently, we jumped to Systemverilog methodology for verification and had a training on Systemverilog, as well. An extensive training which covered design aspects in a day and then verification aspects in next 2 days. 

Some of the links on Systemverilog which can be very helpful -

1. Asicguru -> A very nice tutorial on Systemverilog.
2. Testbench.in -> A website which has many pages on Systemverilog and describes concepts pretty well. It also has very good tutorial on UVM methodology for verification.
3. A tutorial on Systemverilog -> A tutorial which can be referenced.
4. A quick go through on Systemverilog -> pretty nice short and sweet tutorial.

Key features of Systemverilog are -

    -> Classes
    -> Interfaces
         -> Clocking blocks
    -> Events - more what is available in Verilog.
    -> SV Assertions
    -> Coverage
    -> SV Randomization

Later, A training on UVM was also run for the team. UVM, which is becoming hot for the verification basically integrate the verification methodologies by different EDA vendors e.g. Mentor and Cadence. It seems that Synopsys also has jumped to join the UVM although with some pre-conditions that few parts of VMM need to be adapted well in UVM. At this point of time, I couldn't get deeply what and how, VMM could differentiate things.

So Systemverilog, the design aspects have got some changes which are good for designers. Main change is w.r.t. the operators. In verilog, there haven't been support for increment (++) and decrement(--) or even the assignment operations e.g. (+=). The wild equality operators (=== and !==) act like the comparisons in a casex statement, with X and Z values meaning “don’t care”.