SystemVerilog for verification

Recently, we jumped to Systemverilog methodology for verification and had a training on Systemverilog, as well. An extensive training which covered design aspects in a day and then verification aspects in next 2 days. 

Some of the links on Systemverilog which can be very helpful -

1. Asicguru -> A very nice tutorial on Systemverilog.
2. Testbench.in -> A website which has many pages on Systemverilog and describes concepts pretty well. It also has very good tutorial on UVM methodology for verification.
3. A tutorial on Systemverilog -> A tutorial which can be referenced.
4. A quick go through on Systemverilog -> pretty nice short and sweet tutorial.

Key features of Systemverilog are -

    -> Classes
    -> Interfaces
         -> Clocking blocks
    -> Events - more what is available in Verilog.
    -> SV Assertions
    -> Coverage
    -> SV Randomization